1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a method for fabricating capacitors in a DRAM device.
2. Background of the Invention
Modern VLSI technology allows integration of 4 Giga bit DRAM, which requires the feature length of the device dimension to be less than 0.15 .mu.m. Also, the contact hole size and the mis-alignment margin has to be reduced. The self-aligned contact process has been developed to reduce the contact hole size and to increase the degree of alignment in photolithography. The self-aligned contact process also reduces the contact resistance because the whole contact area is effective regardless of the reduction of the contact hole size.
The conventional process of fabricating capacitors in a semiconductor device will be described with reference to FIGS. 1A to 1D, as follows:
Referring to FIG. 1A, a semiconductor substrate 10 is firstly provided with shallow trench isolations 12 to define active and inactive regions, and then covered with a first oxide layer 14. The first oxide layer 14 is selectively etched according to a contact hole patterning mask to form the self-aligned contact holes for storage node contact pads 16. The storage node contact pads 16 are formed by planarizing a polysilicon layer deposited over the substrate by CMP (Chernical-Mechanical Polishing) until the first oxide layer 14 is exposed. Thus, the storage node contact pad 16 is electrically connected to the substrate 10. Subsequently, a second oxide layer 18 is deposited over the first oxide layer 14 embedding the storage node contact pads 16 as shown in FIG. 1B, then etched according to a bit line contact hole patterning mask to form bit line contact holes (not shown in the drawings). A polysilicon layer is deposited over the second oxide layer 18, then etched until the second oxide layer 18 is exposed to form bit line contact pads (not shown in the drawings). Additionally formed on the second oxide layer 18 are the bit lines 20 electrically connected to the bit line contact pads. The second oxide layer 18 and the bit lines 20 are covered sequentially with a third oxide layer 22, a nitride layer 24 and a fourth oxide layer 26. In this case, the nitride layer 24 serves to protect the bit lines 20 from being oxidized by O.sub.2 contained in the dielectric layer of the capacitor produced in the subsequent process steps.
Referring to FIG. 1C, storage node contact holes 27 are formed by sequentially etching the fourth oxide layer 26, nitride layer 24, third oxide layer 22 and second oxide layer 18 according to a storage node contact patterning mask until the upper surfaces of the storage node contact pads 16 are exposed. Referring to FIG. 1D, a polysilicon layer is deposited over the fourth oxide layer 26 containing the storage node contact holes 27. This polysilicon layer is patterned according to a storage node patterning mask to form the storage nodes 30 integrated with the storage node contacts 28. The storage node 30 is formed with a thickness of more than 10000.ANG.. Finally, sequentially deposited over the fourth oxide layer containing the storage nodes 30 are the dielectric layer 32 and the upper electrode 34 of the capacitor.
With the increase in integration size, i.e., the number of transistors and other electronic components packed onto a single IC chip, the misalignment margin is reduced to less than 40 nm between the self-aligned contact pad and storage node contact, storage node contact and storage node, storage node contact and bit line, and storage node contact and gate. Moreover, metallization after forming the storage nodes should suffer considerably reduced margins for DOF (Depth of Focus) due to the level difference of more than 10000.ANG. between the cell and core.